// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary design header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.

#ifndef VERILATED_VSIMTOP_H_
#define VERILATED_VSIMTOP_H_  // guard

#include "verilated_heavy.h"
#include "VSimTop__Dpi.h"

//==========

class VSimTop__Syms;
class VSimTop_VerilatedVcd;
class VSimTop___024unit;


//----------

VL_MODULE(VSimTop) {
  public:
    // CELLS
    // Public to allow access to /*verilator_public*/ items;
    // otherwise the application code can consider these internals.
    VSimTop___024unit* __PVT____024unit;

    // PORTS
    // The application code writes and reads these signals to
    // propagate new values into/out from the Verilated model.
    VL_IN8(clock,0,0);
    VL_IN8(reset,0,0);
    VL_IN8(io_perfInfo_clean,0,0);
    VL_IN8(io_perfInfo_dump,0,0);
    VL_OUT8(io_uart_out_valid,0,0);
    VL_OUT8(io_uart_out_ch,7,0);
    VL_OUT8(io_uart_in_valid,0,0);
    VL_IN8(io_uart_in_ch,7,0);
    VL_IN8(io_memAXI_0_aw_ready,0,0);
    VL_OUT8(io_memAXI_0_aw_valid,0,0);
    VL_OUT8(io_memAXI_0_aw_bits_prot,2,0);
    VL_OUT8(io_memAXI_0_aw_bits_id,3,0);
    VL_OUT8(io_memAXI_0_aw_bits_user,0,0);
    VL_OUT8(io_memAXI_0_aw_bits_len,7,0);
    VL_OUT8(io_memAXI_0_aw_bits_size,2,0);
    VL_OUT8(io_memAXI_0_aw_bits_burst,1,0);
    VL_OUT8(io_memAXI_0_aw_bits_lock,0,0);
    VL_OUT8(io_memAXI_0_aw_bits_cache,3,0);
    VL_OUT8(io_memAXI_0_aw_bits_qos,3,0);
    VL_IN8(io_memAXI_0_w_ready,0,0);
    VL_OUT8(io_memAXI_0_w_valid,0,0);
    VL_OUT8(io_memAXI_0_w_bits_strb,7,0);
    VL_OUT8(io_memAXI_0_w_bits_last,0,0);
    VL_OUT8(io_memAXI_0_b_ready,0,0);
    VL_IN8(io_memAXI_0_b_valid,0,0);
    VL_IN8(io_memAXI_0_b_bits_resp,1,0);
    VL_IN8(io_memAXI_0_b_bits_id,3,0);
    VL_IN8(io_memAXI_0_b_bits_user,0,0);
    VL_IN8(io_memAXI_0_ar_ready,0,0);
    VL_OUT8(io_memAXI_0_ar_valid,0,0);
    VL_OUT8(io_memAXI_0_ar_bits_prot,2,0);
    VL_OUT8(io_memAXI_0_ar_bits_id,3,0);
    VL_OUT8(io_memAXI_0_ar_bits_user,0,0);
    VL_OUT8(io_memAXI_0_ar_bits_len,7,0);
    VL_OUT8(io_memAXI_0_ar_bits_size,2,0);
    VL_OUT8(io_memAXI_0_ar_bits_burst,1,0);
    VL_OUT8(io_memAXI_0_ar_bits_lock,0,0);
    VL_OUT8(io_memAXI_0_ar_bits_cache,3,0);
    VL_OUT8(io_memAXI_0_ar_bits_qos,3,0);
    VL_OUT8(io_memAXI_0_r_ready,0,0);
    VL_IN8(io_memAXI_0_r_valid,0,0);
    VL_IN8(io_memAXI_0_r_bits_resp,1,0);
    VL_IN8(io_memAXI_0_r_bits_last,0,0);
    VL_IN8(io_memAXI_0_r_bits_id,3,0);
    VL_IN8(io_memAXI_0_r_bits_user,0,0);
    VL_IN64(io_logCtrl_log_begin,63,0);
    VL_IN64(io_logCtrl_log_end,63,0);
    VL_IN64(io_logCtrl_log_level,63,0);
    VL_OUT64(io_memAXI_0_aw_bits_addr,63,0);
    VL_OUT64(io_memAXI_0_ar_bits_addr,63,0);
    VL_OUT64(io_memAXI_0_w_bits_data[4],63,0);
    VL_IN64(io_memAXI_0_r_bits_data[4],63,0);

    // LOCAL SIGNALS
    // Internals; generally not touched by application code
    // Anonymous structures to workaround compiler member-count bugs
    struct {
        CData/*2:0*/ SimTop__DOT__aw_prot;
        CData/*0:0*/ SimTop__DOT__aw_user;
        CData/*0:0*/ SimTop__DOT__aw_lock;
        CData/*3:0*/ SimTop__DOT__aw_cache;
        CData/*3:0*/ SimTop__DOT__aw_qos;
        CData/*3:0*/ SimTop__DOT__aw_region;
        CData/*0:0*/ SimTop__DOT__w_user;
        CData/*0:0*/ SimTop__DOT__ar_valid;
        CData/*2:0*/ SimTop__DOT__ar_prot;
        CData/*0:0*/ SimTop__DOT__ar_user;
        CData/*0:0*/ SimTop__DOT__ar_lock;
        CData/*3:0*/ SimTop__DOT__ar_cache;
        CData/*3:0*/ SimTop__DOT__ar_qos;
        CData/*3:0*/ SimTop__DOT__ar_region;
        CData/*0:0*/ SimTop__DOT__r_hs;
        CData/*0:0*/ SimTop__DOT__b_hs;
        CData/*0:0*/ SimTop__DOT__mem_read;
        CData/*2:0*/ SimTop__DOT__exe_s1;
        CData/*0:0*/ SimTop__DOT__mem_fetched;
        CData/*0:0*/ SimTop__DOT__axi_write_ready;
        CData/*0:0*/ SimTop__DOT__axi_read_valid;
        CData/*1:0*/ SimTop__DOT__axi_size;
        CData/*7:0*/ SimTop__DOT__axi_write_mask;
        CData/*3:0*/ SimTop__DOT__axi_r_id_o;
        CData/*0:0*/ SimTop__DOT__mem_write;
        CData/*0:0*/ SimTop__DOT__axi_r_hs_o;
        CData/*0:0*/ SimTop__DOT__mtimecmp_open;
        CData/*0:0*/ SimTop__DOT__mtime_open;
        CData/*0:0*/ SimTop__DOT__clint_skip;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_axi_rw__DOT__aw_hs;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_axi_rw__DOT__w_hs;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_axi_rw__DOT__ar_hs;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_axi_rw__DOT__r_done;
        CData/*1:0*/ SimTop__DOT__ysyx_210448_u_axi_rw__DOT__w_state;
        CData/*1:0*/ SimTop__DOT__ysyx_210448_u_axi_rw__DOT__r_state;
        CData/*7:0*/ SimTop__DOT__ysyx_210448_u_axi_rw__DOT__len;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_axi_rw__DOT__len_incr_en;
        CData/*3:0*/ SimTop__DOT__ysyx_210448_u_axi_rw__DOT__addr_end;
        CData/*7:0*/ SimTop__DOT__ysyx_210448_u_axi_rw__DOT__axi_len;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_axi_rw__DOT__rw_ready;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_axi_rw__DOT__rw_ready_en;
        CData/*1:0*/ SimTop__DOT__ysyx_210448_u_axi_rw__DOT__rw_resp;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_axi_rw__DOT__clint_skip_ready;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__id_exe_bubble;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__pc_write;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__if_stop;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__if_fetched;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__if_clk;
        CData/*6:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__id_b_imm;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__id_ena1;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__id_ena2;
        CData/*4:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__id_rs1;
        CData/*4:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__id_rs2;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__id_open;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_open;
        CData/*4:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__rs1;
        CData/*4:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__rs2;
        CData/*6:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__id_opcode_id;
        CData/*4:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_rd;
        CData/*6:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_opcode;
        CData/*6:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_b_imm;
        CData/*6:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_s_imm;
        CData/*4:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_s_imm_s;
        CData/*4:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_i_imm_i;
    };
    struct {
        CData/*4:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_b_imm_b;
        CData/*5:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_w_shamt;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_s2;
        CData/*5:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__shamt;
        CData/*4:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_zimm;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_csr_read;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_csr_write;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_pc_write;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_w_ena;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_skip;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_open;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_mem_en;
        CData/*6:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_opcode;
        CData/*6:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_s_imm;
        CData/*4:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_s_imm_s;
        CData/*2:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_s1;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_w_ena;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_csr_read;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_csr_write;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_skip;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_ok;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_skip;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_open;
        CData/*4:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_rd;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_wb_en;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_w_ena;
        CData/*4:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_rd;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_read;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_csr_write;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_csr_read;
        CData/*6:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_opcode;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__csr_skip;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__id_csr_skip;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_csr_skip;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_csr_skip;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_csr_skip;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__c_interrupt;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__csr_pc_write;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__id_fetched;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_fetched;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_fetched;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__if_axi_stop;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_mem_read;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_write;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__l_double;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__close;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_close;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__if_mem_read;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__id_mem_read;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_mem_read;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_mem_read;
        CData/*2:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__s3;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_write_ready;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_write_ready;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_mem_write;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__if_mem_write;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__id_mem_write;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__if_w_ena;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__id_w_ena;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ld;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__clock_interrupt;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__cmt_wen;
        CData/*7:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__cmt_wdest;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__cmt_valid;
    };
    struct {
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__trap;
        CData/*7:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__trap_code;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__skip;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__interrupt_ready1;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__interrupt_ready2;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__interrupt;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__csr;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__inst_valid;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mstatus_mie;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mstatus_mpie;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__interrupt_mie;
        CData/*1:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mstatus_fs;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__imm1;
        CData/*7:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__imm2;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__imm3;
        CData/*5:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__imm5;
        CData/*3:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__imm6;
        CData/*5:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__sra_imm;
        CData/*4:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__sra_imm_w;
        CData/*4:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__sll_imm;
        CData/*5:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__sll_imm_sll;
        CData/*5:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__srl_imm;
        CData/*4:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__srl_imm_w;
        CData/*7:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__printf;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__mem_read_open;
        CData/*2:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_mem_stage__DOT__s5;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__w_ena;
        CData/*4:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__w_rd;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_CSR__DOT__interrupt_ready1;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_CSR__DOT__interrupt;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_CSR__DOT__pc_write_ready;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_CSR__DOT__wb_stage;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_CSR__DOT__pc_jump;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_CSR__DOT__mstatus_mie;
        CData/*0:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_CSR__DOT__mstatus_mpie;
        CData/*1:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_CSR__DOT__mstatus_fs;
        SData/*11:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__id_csr;
        SData/*11:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_j_imm_j;
        SData/*11:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_i_imm;
        SData/*11:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_I_imm;
        SData/*11:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_w_imm;
        SData/*11:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_csr;
        SData/*11:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_I_imm;
        SData/*11:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_csr;
        SData/*11:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_csr;
        SData/*11:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__exe_b_imm_b_b;
        SData/*11:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__s_s;
        SData/*9:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__imm4;
        SData/*11:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_mem_stage__DOT__s_s;
        SData/*11:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_mem_stage__DOT__mem_I_imm_I;
        IData/*31:0*/ SimTop__DOT__if_inst;
        VlWide<4>/*127:0*/ SimTop__DOT__ysyx_210448_u_axi_rw__DOT__mask;
        IData/*31:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__if_inst_if;
        IData/*31:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst;
        IData/*31:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__id_inst_id;
        IData/*31:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_inst;
        IData/*19:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_u_imm;
        IData/*19:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_j_imm;
        IData/*31:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_inst;
        IData/*31:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_inst;
        IData/*31:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__cmt_inst;
        IData/*31:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__intrNO;
        IData/*31:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__cause;
        IData/*19:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__jal_imm;
    };
    struct {
        IData/*31:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__srlw;
        IData/*31:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__sraw;
        QData/*63:0*/ SimTop__DOT__w_data;
        QData/*63:0*/ SimTop__DOT__if_addr;
        QData/*63:0*/ SimTop__DOT__axi_data_read;
        QData/*63:0*/ SimTop__DOT__axi_read_addr;
        QData/*63:0*/ SimTop__DOT__axi_write_data;
        QData/*63:0*/ SimTop__DOT__axi_write_addr;
        QData/*63:0*/ SimTop__DOT__mem_read_data;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_axi_rw__DOT__axi_r_data_l;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__pc_add;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__if_pc;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__if_pc_if;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__id_pc;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__id_pc_id;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_pc;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_op1;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_op2;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_t;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_csr_data;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_data;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_pc;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_op1;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_op2;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_data;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_csr_data;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mem_read_data;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_pc;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_data;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_read_data;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__wb_csr_data;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__t;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mstatus;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mepc;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mtvec;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mcause;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mip;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mie;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mcause_data;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mstatus_data;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__rmstatus;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mcycle;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mscratch;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__sstatus;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__exe_pc_add;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mhartid;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__csr_pc_add;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__rdata;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__cmt_wdata;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__cmt_pc;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__cycleCnt;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__instrCnt;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mtvec_diff;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mstatus_diff;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__sstatus_diff;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mepc_diff;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mcause_diff;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mip_diff;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mie_diff;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mscratch_diff;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mcause_arch;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mhartid_diff;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__rmstatus_diff;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mepc_exe;
    };
    struct {
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mstatus_diff_diff;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__mret;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_if_stage__DOT__addr;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_if_stage__DOT__if_inst_data;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__exe_u_imm_u;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__exe_b_imm_b_b_b;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__sllw;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__csr_zimm;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_exe_stage__DOT__mepc_reserve;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__mtimecmp;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__mtime;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_CSR__DOT__pc_add_ready;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_CSR__DOT__mepc_exe;
        QData/*63:0*/ SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__w_data;
        VlUnpacked<QData/*63:0*/, 32> SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_o;
        VlUnpacked<QData/*63:0*/, 32> SimTop__DOT__ysyx_210448_u_cpu__DOT__regs_diff;
        VlUnpacked<QData/*63:0*/, 32> SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT__ysyx_210448_Regfile__DOT__regs;
    };

    // LOCAL VARIABLES
    // Internals; generally not touched by application code
    CData/*0:0*/ __Vclklast__TOP__clock;
    VlUnpacked<QData/*63:0*/, 32> SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellinp__ysyx_210448_Pause__regs_o;
    VlUnpacked<QData/*63:0*/, 32> SimTop__DOT__ysyx_210448_u_cpu__DOT____Vcellout__ysyx_210448_wb_stage__regs_o;
    VlUnpacked<QData/*63:0*/, 32> SimTop__DOT__ysyx_210448_u_cpu__DOT__ysyx_210448_wb_stage__DOT____Vcellout__ysyx_210448_Regfile__regs_o;
    VlUnpacked<CData/*0:0*/, 128> __Vtablechg1;
    VlUnpacked<CData/*0:0*/, 64> __Vtablechg2;
    VlUnpacked<CData/*0:0*/, 4> __Vm_traceActivity;
    static VlUnpacked<CData/*1:0*/, 128> __Vtable1_SimTop__DOT__ysyx_210448_u_axi_rw__DOT__w_state;
    static VlUnpacked<CData/*1:0*/, 64> __Vtable2_SimTop__DOT__ysyx_210448_u_axi_rw__DOT__r_state;

    // INTERNAL VARIABLES
    // Internals; generally not touched by application code
    VSimTop__Syms* __VlSymsp;  // Symbol table

    // CONSTRUCTORS
  public:
    VL_UNCOPYABLE(VSimTop);  ///< Copying not allowed
  public:
    /// Construct the model; called by application code
    /// If contextp is null, then the model will use the default global context
    /// If name is "", then makes a wrapper with a
    /// single model invisible with respect to DPI scope names.
    VSimTop(VerilatedContext* contextp, const char* name = "TOP");
    VSimTop(const char* name = "TOP")
      : VSimTop(nullptr, name) {}
    /// Destroy the model; called (often implicitly) by application code
    ~VSimTop();
    /// Trace signals in the model; called by application code
    void trace(VerilatedVcdC* tfp, int levels, int options = 0);

    // API METHODS
    /// Return current simulation context for this model.
    /// Used to get to e.g. simulation time via contextp()->time()
    VerilatedContext* contextp();
    /// Evaluate the model.  Application must call when inputs change.
    void eval() { eval_step(); }
    /// Evaluate when calling multiple units/models per time step.
    void eval_step();
    /// Evaluate at end of a timestep for tracing, when using eval_step().
    /// Application must call after all eval() and before time changes.
    void eval_end_step() {}
    /// Simulation complete, run final blocks.  Application must call on completion.
    void final();

    // INTERNAL METHODS
    static void _eval_initial_loop(VSimTop__Syms* __restrict vlSymsp);
    void __Vconfigure(VSimTop__Syms* symsp, bool first);
  public:
    static QData _change_request(VSimTop__Syms* __restrict vlSymsp);
    static QData _change_request_1(VSimTop__Syms* __restrict vlSymsp);
  public:
    static void _combo__TOP__3(VSimTop__Syms* __restrict vlSymsp);
    static void _combo__TOP__7(VSimTop__Syms* __restrict vlSymsp);
  public:
    static void _ctor_var_reset(VSimTop* self) VL_ATTR_COLD;
  public:
    static void _eval(VSimTop__Syms* __restrict vlSymsp);
  public:
#ifdef VL_DEBUG
    void _eval_debug_assertions();
#endif  // VL_DEBUG
  public:
    static void _eval_initial(VSimTop__Syms* __restrict vlSymsp) VL_ATTR_COLD;
    static void _eval_settle(VSimTop__Syms* __restrict vlSymsp) VL_ATTR_COLD;
    static void _initial__TOP__2(VSimTop__Syms* __restrict vlSymsp) VL_ATTR_COLD;
    static void _multiclk__TOP__8(VSimTop__Syms* __restrict vlSymsp);
    static void _sequent__TOP__4(VSimTop__Syms* __restrict vlSymsp);
    static void _sequent__TOP__5(VSimTop__Syms* __restrict vlSymsp);
    static void _settle__TOP__1(VSimTop__Syms* __restrict vlSymsp) VL_ATTR_COLD;
    static void _settle__TOP__6(VSimTop__Syms* __restrict vlSymsp) VL_ATTR_COLD;
  public:
    static void traceChgSub0(void* userp, VerilatedVcd* tracep);
    static void traceChgTop0(void* userp, VerilatedVcd* tracep);
    static void traceCleanup(void* userp, VerilatedVcd* /*unused*/);
    static void traceFullSub0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD;
    static void traceFullTop0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD;
    static void traceInitSub0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD;
    static void traceInitTop(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD;
    void traceRegister(VerilatedVcd* tracep) VL_ATTR_COLD;
    static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD;
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);

//----------


#endif  // guard
